In a clock signal frequency dividing circuit which divides the frequency of a clock signal having an arbitrary frequency to generate a clock signal having a lower frequency, a frequency dividing circuit (integer frequency dividing circuit) in which the frequency division ratio, i.e., the ratio of the frequencies of clock signals before and after the frequency division is 1/M (M is an integer) can be easily implemented using a counter.
There is proposed a frequency dividing circuit capable of dividing the frequency even at a frequency division ratio of a rational number given by N/M (N is a positive integer and M is a positive integer larger than N) (see, e.g., Japanese Patent Laid-Open Nos. 2005-45507 and 2006-148807). According to these related arts, the value N for setting the numerator of the frequency division ratio is accumulated in every cycle of an input clock signal. If the sum becomes larger than the value M for setting the denominator of the frequency division ratio, M is subtracted from the sum. By referring to the sum, the clock pulses of the input clock signal are appropriately masked (thinned), implementing rational number frequency division.